The design and fabrication of very large scale integrated (VLSI) and ultra large scale integrated (ULSI) circuits is a labor-intensive and error-prone process. Furthermore, with the increasing complexity and component density of such circuitry on a single chip, the amount of chip area devoted to mere interconnection of components becomes a limiting factor in their design. The design of each chip is viewed as a custom effort and therefore consumes enormous time, even though much of the circuitry on the chip is directly derived from existing chips. Additionally, straightforward expansion of the circuitry, either in terms of the number of signals that can be handled in parallel, or in the number of components included on the chip, requires a difficult custom design effort. This derives from the need to consider race conditions, critical timing paths and hangup states for each modification of the circuit.
Prior art circuits also require additional consideration of how to selectively conduct signals from various components on the chip to and from other components. Typically, a multiplexer element is placed at the input and/or output of particular components to select which signal(s) will be applied to or conducted away from the component. The use of such multiplexer is an example of costly custom design requirements of the prior art.